1. Technical Field
The present invention generally relates to integrated circuits (ICs). More particularly, the present invention relates to ICs incorporating dynamic or domino logic circuits.
2. Glossary of Terms
Bulk-CMOS refers to Complementary Metal Oxide Semiconductor and refers to a design and fabrication technology for semiconductors.
SOI where Insulator is Oxide or nitride of Silicon and the like or Sapphire. The SOI field effect transistor n-type has a parallel parasitic bipolar NPN transistor associated with it. The drain of the n-type is equivalent to the collector of the parasitic bipolar transistor. The source of the n-type is equivalent to the emitter of the parasitic bipolar transistor. The body of the n-type becomes charged by induced leakage whenever the drain and source terminals are held at a high potential. If the source is dropped to a low potential the trapped charged in the body causes a current to flow from the base of the parasitic bipolar transistor. This causes a current to flow in the collector that is parallel to a current flowing in the drain. This action may discharge the drain node of a dynamic circuit and may result in erroneous evaluation. The SOI device may be strained by introducing another material with different atomic size than Silicon e.g. Germanium and the like.
A Metal Oxide Semiconductor (MOS) transistor has 2 electrodes referred to as the source and the drain and a control electrode as the gate. A transistor has a bulk connection which may be floating e.g. in SOI.
N-type is a Metal Oxide Semiconductor (MOS) transistor with electrons as majority carriers.
P-type is a Metal Oxide Semiconductor (MOS) transistor with holes as majority carriers
Primitives are technology independent gates e.g. AND gates, OR gates, NOT etc.
NAND gate is inversion of AND and NOR is inversion of OR.
A Register Transfer Level Description is a high level abstraction of a logic design. It comprises logic functions to be implemented in an integrated circuit. Interface constraints and a technology data-base may be specified. An example of a language that may be used for RTL description is VHDL or Verilog etc.
.lib is the well-known Synopsys library format.
Expressions are the product of parsing register transfer level statements and may be utilized as the starting point in a logic description.
Digital design Synthesis is used to mean the synthesis of a technology dependent model from a register transfer level description or from interconnected functional blocks to result in standard-cell mapped design from a target library, or result in a combination of standard-cell mapped design from a target library and a transistor level representation for part or all of the input design specification.
Under DeMorgan's theorem, a NAND gate with inverted inputs performs an OR function and a NOR gate with inverted inputs performs an AND function.
A short-circuit occurs when there is a path of zero or almost zero resistance between a first known voltage level and a second known voltage level.
A non-inverting node has no inversion e.g. AND, OR and the like or a combination of these.
An inverting node has inversion e.g. NAND, NOR, NOT and the like or a combination of these.
Domino logic circuits are discussed in “High-Speed Compact Circuits with CMOS”, Krambeck et al., IEEE Journal of Solid-State Circuits, Vol. SC-17, No. 3, June 1982, pp. 614-619, and “High-Speed CMOS Design Styles”, Kluwer Academic Publishers, Boston, 1998, pp. 93-98 and U.S. Pat. No. 5,291,076 issued to Bridges et. al. on Mar. 1, 1994 and U.S. Pat. No. 6,225,826 issued to Krishnamurthy et. al on May 1, 2001 and are dynamic in nature with precharge and evaluation clock to provide output and/or complementary output.
3. Description of the Related Art
Digital circuits often require true and complementary boolean logic functions. Dynamic or Domino circuits require conversion to non-inverting only stages and may result in some duplication resulting in increased area and power consumption. To avoid this duplication, a dual output implementation (including true and/or complementary versions of the domino stage) is used.
For example, A dynamic cascode switching arrangement as prior art of U.S. Pat. No. 5,291,076 issued to Bridges et. al. on Mar. 1, 1994 is depicted in FIG. 1 of a precharge device 28. Precharge device 28 is implemented as a NOR gate. This design allows precharge device 28 to have a large number of input signals without reducing its performance. Precharge device 28 has a CLOCK and a transistor tree 29 and two nodes 30 and 32. Tree 29 is connected between nodes 30 and 32 and contains logic circuits operable to electrically short-circuit nodes 30 and 32 together given a predetermined set of inputs as will be described below. The transistor tree 29 contains three transistors Q14, Q15, and Q16 connected in parallel between nodes 30 and 32. The gates of transistors Q14, Q15 and Q16 are connected to the input signals A.sub.1, A.sub.2 and A.sub.3, respectively. The drains of transistors Q14, Q15, and Q16 are connected to node 30. The sources of transistors Q14, Q15, and Q16 are connected to node 32.
Precharge device 28 also has two clocking transistors Q17 and Q18, an evaluate transistor Q19 and a screening transistor Q20. The gates of clocking transistors Q17 and Q18 and evaluate transistor Q19 are connected to a periodic timing signal, CLOCK. The drains of clocking transistors Q17 and Q18 are connected to a voltage supply. V.sub.DD. The source of clocking transistor Q17 is connected to node 30. The source of clocking transistor Q18 is connected to an output node 34. Evaluate transistor Q19 has its drain and source connected to node 32 and to ground, respectively. Screening transistor Q20 has its gate connected to node 30, its drain connected to output node 34 and its source connected to node 32.
Precharge device 28 may have two latching transistors Q21 and Q22 to improve the resistance of precharge device 28 to inherent circuit instabilities. Both of the drains of latching transistors Q21 and Q22 are connected to V.sub.DD. The source and gate of latching transistor Q21 are connected to nodes 30 and 34, respectively. Conversely, the source and gate of latching transistor Q22 are connected to nodes 34 and 30, respectively.
The output of precharge device 28, OUTPUT*, is generated by the voltage at node 34 inverted and buffered by an inverter 36. An inverter 37 connected to node 30 generates the signal OUTPUT. As depicted, all transistors in precharge device 28 are n-channel devices with the exception of clocking transistors Q17 and Q18 and latching transistors Q21 and Q22. Clocking transistors Q17 and Q18 and latching transistors Q21 and Q22 are p-channel devices.
Node 30 is discharged if any of the inputs A.sub.1, A.sub.2, and A.sub.3 are a logic high which is input to inverter 36. However, one skilled in the art will readily appreciate the wide variety of applications for precharge device 28 with suitably modified transistor trees. The precharge device 28, has two stages, the precharge and evaluate stages correspond to a low and a high voltage on CLOCK, respectively.
In operation, precharge device 28 precharges nodes 30 and 34 to a known or predetermined voltage level when the input CLOCK is low. In the illustrated form, nodes 30 and 34 are precharged to V.sub.DD. The output from inverters 36 and 37 are therefore initially low. Transistor Q20 causes a voltage drop between nodes 34 and 32 of V.sub.TH, one transistor threshold voltage. Node 32 is therefore initially at a voltage of (V.sub.DD−V.sub.TH). When the input CLOCK switches high, precharge device 28 evaluates the voltage present on node 30. In the evaluation stage if inputs through transistors Q14 or Q15 or Q16 result in a conductive path, the voltage at node 30 is discharged to a second known or predetermined voltage level through clocking transistor Q19. In the illustrated form, node 30 is discharged to ground, V.sub.SS. The voltage on node 32 also drops to ground, V.sub.SS as the input CLOCK places clocking transistor Q19 in a conducting state. As the voltage on node 30 drops, screening transistor Q20 ceases to conduct. The non conducting state of screening transistor Q20 prevents node 34 from discharging, maintaining the low output from inverter 36. The low voltage level on node 30, however, causes OUTPUT to switch to high.
In case that inputs to transistors Q14, Q15 or Q16 do not result in a conductive path in the evaluation stage. The precharge device, 28 implemented as a NOR gate is the combination of inputs, A.sub.1, A.sub.2, and A.sub.3 that does not discharge node 30. In this state, precharge device 28 outputs a logic high signal through inverter 36.
As described above, precharge device 28 precharges nodes 30 and 34 to V.sub.DD, precharges node 32 to (V.sub.DD−V.sub.TH) and outputs a logic low on inverters 36 and 37 when the input CLOCK is low. When the input CLOCK switches high, precharge device 28 evaluates the voltage present on node 30. If the inputs do not result in the voltage at node 30 to be discharged to V.sub.SS, ground, a high voltage on node 30 places screening transistor Q20 in a conducting state. Evaluate transistor Q19 is placed in a conducting state by a high CLOCK signal. Node 34 then discharges to ground through screening transistor Q20 and evaluate transistor Q19. Inverter 36 inverts the low voltage on node 34 and outputs a high logic level. Inverter 37 inverts the high voltage at node 30 and continues to output a low logic signal as Node 32 discharges to ground.
In the evaluation stage, one or more of decode transistors Q14, Q15 or Q16 may, discharge node 30 to V.sub.SS, ground. Node 30 discharges after a finite time which depends on the delay associated with the transistor tree 29, evaluation transistor Q19, screening transistor Q20, capacitance on node 30 and the cascade switching arrangement. This finite discharge time for node 30 places latching transistor Q22 into a non-conducting state during this finite time and is unable to supply voltage, V.sub.DD, to node 34. The evaluate transistor Q19 turns on as soon as the CLOCK goes from precharge to evaluate stage. Worst of all, the screening transistor Q20 stays in the ON state for a finite time, giving rise to a glitch on node 34 and nothing to replenish it. Any additional keeper(s) if present also slow down this circuit due to contention on node 34. Further, if node 34 discharges below a certain threshold, inverter 36 would erroneously treat the voltage at node 34 as a logic low resulting an erroneous value on OUTPUT*. Dynamic circuits such as precharge device 28 are particularly susceptible to such erroneous loss of precharge and glitches are not tolerated on OUTPUT* as it may be input to other precharge devices similar to 28.
In another example, dynamic cascade switching arrangement prior art of U.S. Pat. No. 6,225,826 issued to Krishnamurthy et. al. on May 1, 2001 is depicted in FIG. 2 and includes a domino stage 202 including a series of parallel nFET transistors (represented by M42 and M43) that receive a domino stage input signal A1 . . . An. But without an evaluation transistor between the source(s) of A1 . . . An and V.sub.SS whose gate may have been connected to the CLK. In the precharge phase, when CLK is low, a node N1 is pulled high through a pFET transistor M40 and a node N2 is pulled high through a pFET transistor M45. With nodes N1 and N2 high, OUT and OUT* are low through inverters 210 and 212.
In the evaluate phase, CLK is high so that transistors M40 and M45 are off, but transistor M47 is on. If no bit of A1 . . . An is high, node N1 remains high and node N2 is pulled low through transistors M46 and M47. With node N2 low, OUT* is pulled high through inverter 212. If any of A1 . . . An is high, node N1 is pulled low after a finite time which depends on the delay associated with the transistor tree M42 . . . M43, screening transistor M44, capacitance on node N1 and the cascade switching arrangement.
This finite discharge time for node N1 places latching transistor M44 into a non-conducting state during this finite time and is unable to supply voltage, V.sub.DD, to node N2. The evaluate transistor M47 turns on as soon as the CLOCK goes from precharge to evaluate stage. Worst of all, the screening transistor M46 stays in the ON state for a finite time, giving rise to a glitch on node N2 and nothing to replenish it. Any additional keeper(s) if present also slow down this circuit due to contention on node N2. Further, if node 34 discharges below a certain threshold, inverter 212 would erroneously treat the voltage at node N2 as a logic low resulting an erroneous value on OUT*. Dynamic circuits such as precharge device 202 are particularly susceptible to such erroneous loss of precharge and glitches are not tolerated on OUT* as it may be input to other precharge devices similar to 202.
A disadvantage of the prior art is the glitch problem makes the dynamic circuit very vulnerable to erroneous results as the loss of precharge cannot be compensated, while reducing the delay through this dynamic circuit.
Several prior art U.S. patents teach to delay the clock signal to generate a complementary output, e.g. U.S. Pat. No. 6,549,040 issued to Alvandpour et. al on Apr. 15, 2003, U.S. Pat. No. 6,225,826 issued to Krishnamurthy et. al. on May 1, 2001, U.S. Pat. No. 6,377,080 issued to Arnold on Apr. 23, 2002, U.S. Pat. No. 6,492,839 issued to Wang et. al on Dec. 10, 2002 and U.S. Pat. No. 5,892,372 issued to Ciraula et.al on Apr. 6, 1999. It is difficult to provide optimal delay within the semiconductor process variations, any extra delay with additional safety margin will slow down the circuit and shorter delay may result in glitch and race conditions.